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| CS48500 Data Sheet FEATURES Cost-effective, High-performance 32-bit DSP 300,000,000 MAC/S (multiply accumulates per second) Dual MAC cycles per clock 72-bit accumulators are the most accurate in the industry 24k x 32 SRAM, 2k blocks - assignable to data or program Internal ROM contains a variety of configurable sound enhancement feature sets -- 8-channel internal DMA -- Internal watch-dog DSP lock-up prevention -- -- -- -- -- Differentiating from the legacy Cirrus multi-standard, multichannel decoders, this new CS48500 family is still based on the same high-performance 32-bit fixed point DSP Digital Signal Processor core but instead is equipped with much less memory, tailoring it for more cost-effective applications associated with multi-channel and virtual-channel sound enhancements. Target applications are: -- Digital Televisions -- Multimedia Peripherals -- -- -- -- -- iPod(R) Docking Stations Automotive Head Units Automotive Outboard Amplifiers HD-DVD & Blu-ray Disc DVD Receivers PC Speakers DSP Tool Set w/ Private Keys for Protecting Customer IP Configurable Serial Audio Inputs/Outputs -- -- -- -- -- -- Configurable for all input/output types Maximum 32-bit @ 192 kHz Supports 32-bit audio sample I/O between DSP chips TDM input modes (multiple channels on same line) 192 kHz SPDIF transmitter Multi-channel DSD direct stream digital SACD input EN D T IA EL L PH D R I A Ordering Information: See page 23 for ordering information Serial Control 1 GPIO Debug 32-bit DSP P X Y D M A In these applications there are a wide variety of licensable DSP IP codes available today from: FT Watchdog TMR1 TMR2 PLL w TM Supports Two Different Input Fs Sample Rates -- -- -- -- (R) Output can be master or slave Dual processing path capability Input supports dual domain slave clocking Hardware assist time sampling for sample rate conversion Integrated Clock Manager/PLL Cirrus also has developed, or is developing their own royaltyfree versions of popular features sets like Cirrus Bass Manager, Cirrus Dynamic Volume Leveler, Cirrus Original Multichannel Surround, Cirrus Virtual Speaker & Cirrus 3DAudio. The CS48500 is programmed using the Cirrus proprietary DSP ComposerTM GUI development tool. Processing chains may be designed using a drag-and-drop interface to place/utilize functional macro audio DSP primitives. The end result is a software image that is down-loaded to the DSP via serial host or serial boot modes. -- Can operate from external crystal, external oscillator Input Fs Auto Detection Host & Boot via Serial Interface Configurable GPIOs and External Interrupt Input 1.8V Core / 3.3V I/O that are +5V Tolerant Low-power Mode -- "Energy-Star Ready" via low-power mode, 350uW in standby C O S/PDIF 12 Ch PCM Audio Out N 12 Ch. Audio In / 6 Ch. SACD In FI D Advance Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. CONFIDENTIAL DEC '06 DS734A3 (c)Copyright 2006 Cirrus Logic, Inc. CS48500 Data Sheet 32-bit Audio Decoder DSP Family Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com. IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. All equipment manufactured using any Cirrus Logic chip containing enabled CIRCLE SURROUND(R) TECHNOLOGY must carry the Circle Surround(R) logo on the front panel in a manner approved in writing by SRS Labs, Inc., or Valence Technology Ltd. If the Circle Surround(R) logo is printed in users manuals, service manuals or advertisements, it must appear in a form approved in writing by SRS Labs, Inc., or Valence Technology, Ltd. The rear panel of Circle Surround(R) products, users manuals, service manuals, and all advertising must all carry the legends as described in LICENSOR'S most current version of the CIRCLE SURROUND Trademark Usage Manual. SPI is a trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductor. iPod is a registered trademark of Apple Computer, Inc. C Users of any Cirrus Logic chip containing enabled CIRCLE SURROUND TECHNOLOGY(R) (i.e., CIRCLE SURROUND(R) LICENSEES) must first sign a license to purchase production quantities for consumer electronics applications which may be granted upon submission of a preproduction sample to, and the satisfactory passing of performance verification tests performed by SRS Labs, Inc., or Valence Technology Ltd. E-mail requests for performance specifications and testing rate schedule may be made to cslicense@srslabs.com. SRS Labs, Inc. and Valence Technology, Ltd., reserve the right to decline a use license for any submission that does not pass performance specifications or is not in the consumer electronics classification. O SRS, Circle Surround and Trusurround XT are registered trademarks of SRS Labs, Inc. Circle Surround II is a trademark of SRS Labs, Inc. The CIRCLE SURROUND TECHNOLOGY rights incorporated in the Cirrus Logic chip are owned by SRS Labs, Inc. and by Valence Technology Ltd., and licensed to Cirrus Logic, Inc. N DTS is a registered trademark of the Digital Theater Systems, Inc. DTS Neo:6 is a trademark of Digital Theater Systems, Inc. It is hereby notified that a third-party license from DTS is necessary to distribute software of DTS in any finished end-user or ready-to-use final product. FI Dolby, Dolby Digital, Dolby Headphone, Dolby Virtual Speaker, Dolby Headphone, and Pro Logic are registered trademarks of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. 2 D EN D TI EL A L PH D I RA (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL FT DS734A3 CS48500 Data Sheet 32-bit Audio Decoder DSP Family Table of Contents 1. Documentation Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. Code Overlays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. Hardware Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1.1 DSP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1.2 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 On-chip DSP Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.1 Digital Audio Input Port (DAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.2 Digital Audio Output Port (DAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.3 Serial Control Port (I2C(R) or SPITM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.4 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.5 PLL-based Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.6 Hardware Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 DSP I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.1 Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.2 Termination Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.3 Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 Application Code Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Digital DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Power Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Thermal Data (48 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Switching Characteristics-- RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Switching Characteristics -- XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Switching Characteristics -- Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 Switching Characteristics -- Serial Control Port - SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Switching Characteristics -- Serial Control Port - SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 Switching Characteristics -- Serial Control Port - I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 Switching Characteristics -- Serial Control Port - I2C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 Switching Characteristics -- Digital Audio Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14 Switching Characteristics -- DSD Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15 Switching Characteristics -- Digital Audio Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 13 13 14 15 15 16 17 18 19 20 21 22 9. Package Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1 48-pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 C O 8.1 CS48520, 48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2 CS48540, 48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.3 CS48560,48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 N FI 6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8. Device Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DS734A3 D EN D TI EL A L PH D I RA (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL FT 3 CS48500 Data Sheet 32-bit Audio Decoder DSP Family List of Figures Figure 1. RESET Timing .........................................................................................................................14 Figure 2. XTI Timing................................................................................................................................15 Figure 3. Serial Control Port - SPI Slave Mode Timing...........................................................................16 Figure 4. Serial Control Port - SPI Master Mode Timing.........................................................................17 Figure 5. Serial Control Port - I2C Slave Mode Timing ...........................................................................18 Figure 6. Serial Control Port - I2C Master Mode Timing .........................................................................19 Figure 7. Digital Audio Input (DAI) Port Timing Diagram ........................................................................20 Figure 8. Direct Stream Digital - Serial Audio Input Timing.....................................................................21 Figure 9. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode........................21 Figure 10. Digital Audio Output Data, Input and Output Clock Timing....................................................22 Figure 11. Digital Audio Port Timing, MCLK Master Mode .....................................................................22 Figure 12. CS48520, 48-Pin LQFP Pinout ..............................................................................................24 Figure 13. CS48540, 48-Pin LQFP Pinout ..............................................................................................25 Figure 14. CS48560, 48-Pin LQFP Pinout ..............................................................................................26 Figure 15. 48-Pin LQFP Package Drawing .............................................................................................27 List of Tables Table 1. CS48500 Related Documentation...............................................................................................5 Table 2. Device and Firmware Selection Guide........................................................................................8 Table 3. Ordering Information .................................................................................................................23 Table 4. Environmental, Manufacturing, & Handling Information............................................................23 C O N FI 4 D EN D TI EL A L PH D I RA (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL FT DS734A3 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 1. Documentation Strategy The CS48500 Data Sheet describes the CS48500 family of multichannel audio processors. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS48500 family of processors. Document Name CS48500 Data Sheet CS48500 Hardware User's Manual Description This document Includes detailed system design information including Typical Connection Diagrams, BootProcedures, Pin Descriptions, Etc. AN298 - CS48500 Firmware User's Manual DSP Composer User's Manual Table 1. CS48500 Related Documentation The scope of the CS48500 Data Sheet is primarily the hardware specifications of the CS48500 family of devices. This includes hardware functionality, characteristic data, pinout, and packaging information. The intended audience for the CS48500 Data Sheet is the system PCB designer, mcu programmer, and the quality control engineer. C O N FI DS734A3 D EN D TI EL A L PH D I RA (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL Includes detailed firmware design information including signal processing flow diagrams and control API information Includes detailed configuration and usage information for the GUI development tool. FT 5 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 2. Overview The CS48500 DSP Family is designed to provide high-performance post-processing and mixing of ditial audio. The dual clock domain provided on the PCM inputs allows for the mixing of audio streams with different sampling frequencies. The low-power standby preserves battery life for applications which are always on, but not necessarily processing audio, such as automotive audio systems. There are three devices comprising the CS48500 family. The CS48520, CS48540 and CS48560 are differentiated by the number of inputs and outputs available. All DSPs support dual input clock domains and dual audio processing paths. All DSPs are available in a 48-pin QFP package. Please refer to Table 2 on page 8 for the input, output, firmware features of each device. Licenses are required for all of the 3rd party audio processing algorithms listed in Section 3. Please contact your local Cirrus Logic Sales representative for more information. C O N FI 6 D EN D TI EL A L PH D I RA (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL DS734A3 FT 2.1 Licensing CS48500 Data Sheet 32-bit Audio Decoder DSP Family 3. Code Overlays The suite of software available for the CS48500 family consists of an operating system (OS) and a library of overlays. The overlays have been divided into three main groups called Matrix-processors, Virtualizerprocessors, and Post-processors. All software components are defined below: 1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, error concealment, etc. 2. Matrix-processor- Any Module that performs a matrix decode on PCM data to produce more output channels than input channels (2 n channels). Examples are Dolby ProLogic IIx and DTS Neo:6. Generally speaking, these modules increase the number of valid channels in the audio I/O buffer. 3. Virtualizer-processor - Any module that encodes PCM data into fewer output channels than input channels (n 2 channels) with the effect of providing "phantom" speakers to represent the physical audio channels that were eliminated. Examples are Dolby Headphone(R) and Dolby Virtual Speaker(R). Generally speaking, these modules reduce the number of valid channels in the audio I/O buffer. 4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the matrix- or virtualizer-processors. Examples are bass management, audio manager, tone control, EQ, delay, customer-specific effects, etc. The bulk of each overlay is stored in ROM within the CS48500, but a small image is required to configure the overlays and boot the DSP. This small image can either be stored in an external serial FLASH/EEPROM, or downloaded via a host controller through the SPITM/I2C(R) serial port. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a new matrix-processor is selected, the OS, virtualizer-, and post-processors do not need to be reloaded -- only the new matrix-processor (the same is true for the other overlays). Table 2 below lists the firmware available based on device selection. Please refer AN298, CS48500 Firmware User's Manual for the latest listing of application codes and Cirrus FrameworkTM modules available. C O N FI DS734A3 D EN D TI EL A L PH D I RA (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL FT 7 8 C N FI D Suggested Application Chanenel Count Input/Output Digital TV Portable Audio Docking Station Portable DVD DVD Mini / Receiver Multimedia PC Speakers Up to 4 channel in / 4 channel out CS48520 features Plus 8 Channel Car Audio DVD Receiver Up to 8 channel in / 8 channel out Package 48-pin QFP Table 2. Device and Firmware Selection Guide CS48500 Data Sheet 32-bit Audio Decoder DSP Family O Device CS48520-CQZ (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL CS48540-CQZ CS48540-DQZ 48-pin QFP CS48560-CQZ CS48540 features Plus 12 channel Car Audio High-end Digital TV Dual Source/Dual Zone SACD CS48560-DQZ EN D TI EL A L PH D I RA FT Up to 12 channel in /12 channel out 48-pin QFP Note: Refer to AN298 for more information on Software features DS734A3 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 4. Hardware Functional Description 4.1 DSP Core The CS48500 is a single-core DSP with separate X and Y data and P code memory spaces. The DSP core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight 72-bit accumulators, four X- and four Y-data registers, and 12 index registers. The DSP core is coupled to a flexible DMA engine. The DMA engine can move data between peripherals such as the serial control port (SCP), digital audio input (DAI) and digital audio output (DAO), or any DSP core memory, all without the intervention of the DSP. The DMA engine off loads data move instructions from the DSP core, leaving more MIPS available for signal processing instructions. CS48500 functionality is controlled by application codes that are stored in on-board ROM or downloaded to the CS48500 from a host controller or external serial FLASH/EEPROM. The CS48500 is suitable for a variety of audio post-processing applications such as automotive headends, automotive amplifiers, and boom boxes. 4.1.1 DSP Memory The DSP core has its own on-chip data and program RAM and ROM and does not require external memory for post-processing applications. The Y-RAM and P-RAM share a single block of memory that can be configured to make Y and P equal in size, or more memory can be allocated for Y-RAM in 2kword blocks. 4.1.2 DMA Controller C O N FI DS734A3 D The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service intervals for each DMA channel, as well as up to 6 interrupt events, are programmable. EN D TI EL A L PH D I RA (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL Users can develop their applications using DSP Composer to create the processing chain and then compile the image into a series of commands that are sent to the CS48500 through the SCP. The processing application can either load modules (matrix-processors, virtualizers, post-processors) from the DSPs on-board ROM, or custom firmware can be downloaded through the SCP. FT 9 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 4.2 On-chip DSP Peripherals 4.2.1 Digital Audio Input Port (DAI) Each version of the CS48500 support a different number of input channels. Refer toTable 2 on page 8 for more details. The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz. The port is capable of accepting PCM or DSD formats. Up to 32-bit word lengths are supported. DSD is supported and internally converted to PCM before processing. The DAI also supports a time division multiplexed (TDM) one-line data mode, that packs PCM audio on a single data line (the total number possible depends on the ratio of SCLK to LRCLK and the version of chip. For example on the CS48520 only 4 ch of PCM are supported in one line mode and on the CS48560 up to 8 channels are supported.). The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, off-loading the task of monitoring the SPDIF receiver from the host. A time-stamping feature allows the input data to be sample-rate converted via software. 4.2.2 Digital Audio Output Port (DAO) Each version of the CS48500 support a different number of output channels. Refer toTable 2 on page 8 for more details. DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a clock slave if an external MCLK or SCLK/LRCLK source is available. One of the serial audio pins can be reconfigured as a SPDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with embedded clock on a single line). 4.2.3 Serial Control Port (I2C(R) or SPITM) The on-chip serial control port is capable of operating as master or slave in either SPITM or I2C(R) modes. Master/Slave operation is chosen by mode select pins when the CS48500 comes out of reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock speed must always be (Fdclk/2)). The CS48500 serial control port also includes a pin for flow control of the communications interface (#SCP_BSY) and a pin to indicate when the DSP has a message for the host (#SCP_IRQ). 4.2.4 GPIO 4.2.5 PLL-based Clock Generator The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS48500 defaults to running from the external reference frequency and is switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1. C O N FI Many of the CS48500 peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high. 10 D EN D TI EL A L PH D I RA (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL FT DS734A3 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 4.2.6 Hardware Watchdog Timer The CS48500 has an integrated watchdog timer that acts as a "health" monitor for the DSP. The watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS48500 will reset itself in the event of a temporary system failure. In standalone mode (i.e. no host mcu), the DSP will reboot from external FLASH. In slave mode (i.e. host mcu present) a GPIO will be used to signal the host that the watchdog has expired and the DSP should be rebooted and re-configured. 4.3 DSP I/O Description 4.3.1 Multiplexed Pins Many of the CS48500 pins are multi-functional. For details on pin functionality please refer to the CS48500 Hardware User's Manual. 4.3.2 Termination Requirements Mode select pins on the CS48500 are used to select the boot mode upon the rising edge from reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS48500 Hardware User's Manual. 4.3.3 Pads The CS48500 I/Os operate from the 3.3 V supply and are 5 V tolerant. 4.4 Application Code Security The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. Please contact your local Cirrus representative for details. C O N FI DS734A3 D EN D TI EL A L PH D I RA (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL Open-drain pins on the CS48500 must be pulled high for proper operation. Please refer to the CS48500 Hardware User's Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. FT 11 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 5. Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: T = 25 C, CL = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V. 5.1 Absolute Maximum Ratings (GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Parameter DC power supplies: Core supply PLL supply I/O supply |VDDA - VDDIO| Symbol VDD VDDA VDDIO Iin Vfilt Vinio Tstg Min -0.3 -0.3 -0.3 -0.3 -0.3 -65 Max 2.0 3.6 3.6 0.3 Unit V V V V mA V V C Input voltage on PLL_REF_RES Input voltage on I/O pins Storage temperature Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 5.2 Recommended Operating Conditions Parameter DC power supplies: (GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Core supply PLL supply I/O supply |VDDA - VDDIO| EN D TI EL A L PH D I RA Symbol VDD VDDA VDDIO TA Min Typ 1.8 3.3 3.3 0 1.71 3.13 3.13 - CQZ - DQZ 0 - 40 Symbol VIH VIL VILXTI Vhys VOH VOL IIN IIN-PU VDDIO * 0.9 Min 2.0 Typ 0.4 (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL FT 3.6 5.0 150 Max 1.89 3.46 3.46 + 70 + 85 Max 0.8 0.6 VDDIO * 0.1 5 56 Input pin current, any pin except supplies +/- 10 Unit V V V V C Ambient operating temperature Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply. 5.3 Digital DC Characteristics Parameter High-level input voltage Low-level input voltage, XTI (Measurements performed under static conditions.) D Unit V V V V V V A A High-level output voltage (IO = -2mA), except XTI Input leakage current (all digital pins with internal pull-up resistors disabled) Input leakage current (all digital pins with internal pull-up resistors enabled, and XTI) 12 C O Low-level output voltage (IO = 2mA), except XTI N Input Hysteresis FI Low-level input voltage, except XTI DS734A3 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 5.4 Power Supply Characteristics (measurements performed under operating conditions) Parameter Operational Power Supply Current: VDD: Core and I/O operating1 VDDA: PLL operating VDDIO: With most ports operating Total Operational Power Dissipation: Standby Power Supply Current: VDD: Core and I/O not clocked VDDA: PLL halted VDDIO: All connected I/O pins 3-stated by other ICs in system Total Standby Power Dissipation: 1.Dependent on application firmware and DSP clock speed. Min Typ 203 8 27 469 Max Unit mA mA mA mW A A A W 5.5 Thermal Data (48 LQFP) Parameter EN D TI EL A L PH D I RA Symbol Min Typ Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 Thermal Resistance (Junction to Top of Package) Two-layer Board1 Four-layer Board2 ja 63.5 54 jt 0.70 0.64 Notes: 1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20 % of the top & bottom layers. 2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20 % of the top & bottom layers and 0.5-oz. copper covering 90 % of the internal power plane & ground plane layers. j = Ambient Temperature + [ (Power Dissipation in Watts) * ja ] c = j - [ (Power Dissipation in Watts) * jt ] C O N FI 4. To calculate the case temperature for a given power dissipation DS734A3 D 3. To calculate the die temperature for a given power dissipation (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL FT Max - - 100 1 15 350 - Unit C / Watt C / Watt 13 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 5.6 Switching Characteristics-- RESET Parameter RESET# minimum pulse width low All bidirectional pins high-Z after RESET# low Configuration pins setup before RESET# high Configuration pins hold after RESET# high Symbol Trstl Trst2z Trstsu Trsthld Min 1 50 20 Max 100 Unit s ns ns ns HS[3:0] All Bidirectional Pins C O N FI 14 D EN D TI EL A L PH D I RA Trst2z Trstl Trstsu Trsthld Figure 1. RESET Timing (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL FT DS734A3 RESET# CS48500 Data Sheet 32-bit Audio Decoder DSP Family 5.7 Switching Characteristics -- XTI Parameter External Crystal operating frequency XTI period XTI high time XTI low time External Crystal Load Capacitance (parallel resonant) External Crystal Equivalent Series Resistance 1 Symbol Fxtal Tclki Tclkih Tclkil CL ESR Min 10 33.3 13.3 13.3 10 Max 30 100 18 50 Unit MHz ns ns ns pF XTI 5.8 Switching Characteristics -- Internal Clock Parameter Internal DCLK frequency 1 EN D TI EL A L PH D I RA t clkih t clkil Tclki Figure 2. XTI Timing Symbol Fdclk Min CS4852x-CQZ CS4854x-CQZ CS4856x-CQZ CS4852x-DQZ CS4854x-DQZ CS4856x-DQZ Fxtal Fxtal Fxtal Fxtal Fxtal DCLKP CS4852x-CQZ CS4854x-CQZ CS4856x-CQZ CS4852x-DQZ CS4854x-DQZ CS4856x-DQZ 6.7 6.7 6.7 6.7 6.7 6.7 (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL FT Max 150 150 150 150 150 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal 1.CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer's recommendation for load capacitor selection. Unit MHz Internal DCLK period1 FI D ns DS734A3 C 1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset. O N 15 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 5.9 Switching Characteristics -- Serial Control Port - SPI Slave Mode . Parameter SCP_CLK frequency SCP_CLK low time SCP_CLK high time Setup time SCP_MOSI input Hold time SCP_MOSI input SCP_CLK low to SCP_MISO output valid SCP_CLK falling to SCP_IRQ# rising SCP_CS# rising to SCP_IRQ# falling SCP_CLK low to SCP_CS# rising SCP_CS# rising to SCP_MISO output high-Z SCP_CLK rising to SCP_BSY# falling 1 Symbol fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspiirqh tspiirql tspicsh tspicsdz Min 24 20 20 5 5 0 24 - Typical Max 25 8 Units MHz ns ns ns ns ns ns ns ns ns ns ns SCP_CS# falling to SCP_CLK rising 1.The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer. tspicss SCP_CS# 0 EN D TI EL A L PH D I RA 20 tspicbsyl 3*DCLKP+20 tspickl 1 2 6 7 0 5 6 7 tspickh A5 A0 R/W MSB LSB tspidh tspidov MSB tspiirqh LSB tspibsyl SCP_CLK fspisck SCP_MOSI A6 tspidsu D SCP_MISO FI SCP_IRQ# C SCP_BSY# Figure 3. Serial Control Port - SPI Slave Mode Timing O N 16 (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL FT 20 tspicsh tspicsdz tspiirql DS734A3 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 5.10 Switching Characteristics -- Serial Control Port - SPI Master Mode Parameter SCP_CLK frequency 1 2 Symbol fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspicsl tspicsh tspicsx tspidz Min 20 20 9 5 7 - Typical 11*DCLKP + (SCP_CLK PERIOD)/2 Max 25 - Units MHz ns ns ns ns ns ns ns ns ns ns SCP_CS# falling to SCP_CLK rising SCP_CLK low time SCP_CLK high time Setup time SCP_MISO input Hold time SCP_MISO input SCP_CLK low to SCP_MOSI output valid SCP_CLK low to SCP_CS# falling SCP_CLK low to SCP_CS# rising Bus free time between active SCP_CS# EN D TI EL A L PH D I RA 3*DCLKP tspickl 1 2 6 7 0 5 6 7 tspickh A0 R/W tspidov MSB LSB MSB LSB tspidh 11*DCLKP + (SCP_CLK PERIOD)/2 SCP_CLK falling to SCP_MOSI output high-Z 1.The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. 2.SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter . tspicss EE_CS# tspicsl 0 N SCP_MISO O FI SCP_CLK fspisck A6 tspidsu D A5 C SCP_MOSI Figure 4. Serial Control Port - SPI Master Mode Timing DS734A3 (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL FT 8 20 tspicsx tspicsh tspidz 17 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 5.11 Switching Characteristics -- Serial Control Port - I2C Slave Mode Parameter SCP_CLK frequency SCP_CLK low time SCP_CLK high time SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition Bus free time between STOP and START conditions Setup time SCP_SDA input valid to SCP_CLK rising Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid NAK condition to SCP_IRQ# low SCP_CLK rising to SCB_BSY# low SCP_CLK falling to SCP_IRQ# rising 1 Symbol fiicck tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich tiicdov tiicirql Min 1.25 1.25 1.25 1.25 2.5 3 100 20 - Typical Max 400 - Units kHz s s s - s s s ns ns ns ns ns ns EN D TI EL A L PH D I RA tiicirqh 3*DCLKP + 20 tiicbsyl 3*DCLKP + 20 tiicckl tiicr tiicf 6 7 8 0 1 6 7 tiicdov fiicck A0 R/W ACK MSB LSB tiicirqh 1.The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer. tiicckcmd 0 1 SCP_CLK tiicstscl tiicckh A6 FT 18 3*DCLKP + 40 tiicckcmd 8 tiicstp ACK tiicirql tiiccbsyl - tiicbft SCP_SDA SCP_BSY# C 18 O Figure 5. Serial Control Port - I2C Slave Mode Timing (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL N SCP_IRQ# FI tiicsu tiich D DS734A3 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 5.12 Switching Characteristics -- Serial Control Port - I2C Master Mode Parameter SCP_CLK frequency SCP_CLK low time SCP_CLK high time SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition Bus free time between STOP and START conditions Setup time SCP_SDA input valid to SCP_CLK rising Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid 1 Symbol fiicck tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich tiicdov Min 1.25 1.25 1.25 1.25 2.5 3 100 20 - Max 400 - Units kHz s s s - s s s ns ns ns EN D TI EL A L PH D I RA tiicckl tiicr tiicf 6 7 8 0 1 6 7 tiicdov fiicck A0 R/W ACK MSB LSB (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL 1.The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. tiicckcmd 0 1 SCP_CLK tiicstscl tiicckh A6 FT 18 - tiicckcmd 8 tiicstp tiicbft N DS734A3 C O FI tiicsu tiich Figure 6. Serial Control Port - I2C Master Mode Timing D SCP_SDA ACK 19 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 5.13 Switching Characteristics -- Digital Audio Slave Input Port Parameter DAI_SCLK period DAI_SCLK duty cycle Setup time DAI_DATAn Hold time DAI_DATAn Symbol Tdaiclkp tdaidsu tdaidh Min 40 45 10 5 Max 55 Unit ns % ns ns DAI_SCLK tdaidsu tdaidh DAI_DATAn Figure 7. Digital Audio Input (DAI) Port Timing Diagram C O N FI 20 D EN D TI EL A L PH D I RA (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL DS734A3 FT CS48500 Data Sheet 32-bit Audio Decoder DSP Family 5.14 Switching Characteristics -- DSD Slave Input Port Parameter MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency Symbol tsclkl tsclkh (64x Oversampled) (128x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time tsdlrs DSD_SCLK rising to DSD_A or DSD_B hold time tsdh DSD clock to data transition (Phase Modulation mode) tdpm Min 40 78 78 1.024 2.048 20 20 -20 Typ Max 60 3.2 6.4 20 Unit % ns ns MHz MHz ns ns ns Figure 8. Direct Stream Digital - Serial Audio Input Timing O C Figure 9. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode N FI DSD_SC LK (128Fs) DSD_SC LK (64Fs) DSD_A, DSD_B DS734A3 D EN D TI EL A L PH D I RA t dpm t dpm (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL FT 21 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 5.15 Switching Characteristics -- Digital Audio Output Port Parameter DAO_MCLK period DAO_MCLK duty cycle DAO_SCLK period for Master or Slave mode Master Mode (Output A1 1 Symbol Tdaomclk Tdaosclk tdaomsck tdaomstlr tdaomdv Min 40 40 40 40 - Max 60 60 19 Unit ns % ns % ns ns ns DAO_SCLK duty cycle for Master or Slave mode1 Mode)1,2 DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an input DAO_LRCLK delay from DAO_SCLK transition, respectively3 DAO1_DATA[3..0], DAO2_DATA[1..0] delay from DAO_SCLK transition3 Slave Mode (Output A0 Mode)4 DAO1_DATA[3..0], DAO2_DATA[1..0] delay from DAO_SCLK transition3 EN D TI EL A L PH D I RA tdaosdv FT 8 10 15 ns 1.Master mode timing specifications are characterized, not production tested. 2.Master mode is defined as the CS48500 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_LRCLK. 3.This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the data is valid. 4.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source. Tdaomclk DAO_MCLK D FI N O tdaomsck DAO_SCLK tdaomdv , tdaosdv DAOn_DATAn tdaomstlr DAO_LRCLK tdaomstlr C 22 Figure 11. Digital Audio Port Timing, MCLK Master Mode (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL DS734A3 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 6. Ordering Information The CS48500 family part number is described as follows: CS485NI-XYZ where N - Product Number Variant I - ROM ID Number X - Product Grade Y - Package Type Z - Lead (Pb) Free Table 3. Ordering Information Part No. Grade Temp. Range CS48520-CQZ CS48540-CQZ CS48540-DQZ CS48560-CQZ CS48560-DQZ NOTE: Please contact the factory for availability of the -D (automotive grade) package. 7. Environmental, Manufacturing, & Handling Information Model Number Peak Reflow Temp MSL Rating* Table 4. Environmental, Manufacturing, & Handling Information CS48540-CQZ CS48540-DQZ CS48560-CQZ FI D CS48520-CQZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. C O N CS48560-DQZ DS734A3 EN D TI EL A L PH D I RA Commercial Commercial Automotive 0 to +70 C 0 to +70 C -40 to +85 C 0 to +70 C Commercial Automotive -40 to +85 C 260 C 3 7 Days Max Floor Life (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL FT Package 48-pin LQFP 23 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 8. Device Pinout Diagrams 8.1 CS48520, 48-pin LQFP Pinout Diagram GPIO10, SCP__MISO / SDA GPIO6, DAO2 _DATA0, HS3 GPIO11, SCP_CLK GPIO7, HS4 GPIO8, SCP_CS# 38 EN D TI EL A L PH D I RA 23 22 21 20 VDDIO3 37 GPOI12, SCP_IRQ# 39 GNDIO4 40 GPIO13, SCP_BSY#, EE_CS# 41 VDD3 42 CS48520 48 LQFP XTAL_OUT 43 XTI 44 XTO 45 GNDA D 46 PLL_REF_RES 47 FI N VDDA (3.3V) 48 10 11 GPIO0 RESET# GNDIO1 C Figure 12. CS48520, 48-Pin LQFP Pinout 24 (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL GPIO16, DAI1_DATA0 DAI1_LRCLK O DAI1_SCLK VDDIO1 GND1 GND2 TEST DBDA DBCK 12 1 2 3 4 5 6 7 8 9 FT 24 VDDIO2 DAO_SCLK GND3 DAO_LRCLK DAO1_DATA0, HS0 19 GNDIO2 18 GPIO15, DAI2_SCLK 17 GPIO14, DAI2_LRCLK 16 VDD1 15 GPIO17, DAI2_DATA0 14 GPIO2 13 GPIO1 GNDIO3 36 35 33 31 30 28 26 34 32 29 27 25 GPIO18, DAO_MCLK GPIO9, SCP_MOSI GPIO5, XMTA GND4 VDD2 GPIO3, HS1 GPIO4, HS2 DS734A3 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 8.2 CS48540, 48-pin LQFP Pinout Diagram GPIO6, DAO2_DATA0, HS3 GPIO3, DAO1_ DATA1, HS1 GPIO4, DAO1_ DATA2, HS2 GPIO10, SCP__MISO / SDA GNDIO3 36 35 33 31 30 28 26 34 32 29 27 VDDIO3 37 GPIO8, SCP_CS# 38 GPOI12, SCP_IRQ# 39 GNDIO4 40 GPIO13, SCP_BSY#, EE_CS# 41 VDD3 42 XTAL_OUT 43 XTI 44 XTO 45 GNDA 46 D PLL_REF_RES 47 FI VDDA (3.3V) 48 10 11 DAI1_LRCLK RESET# GNDIO1 C O Figure 13. CS48540, 48-Pin LQFP Pinout DS734A3 (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL GPIO16, DAI1_DATA0 GPIO0, DAI1_DATA1 N DAI1_SCLK VDDIO1 GND1 GND2 TEST DBDA DBCK 12 1 2 3 4 5 6 7 8 9 EN D TI EL A L PH D I RA 22 21 20 CS48540 48 LQFP FT 24 VDDIO2 23 DAO_SCLK GND3 DAO_LRCLK DAO1_DATA0, HS0 19 GNDIO2 18 GPIO15, DAI2_SCLK 17 GPIO14, DAI2_LRCLK 16 VDD1 15 GPIO17, DAI2_DATA0 14 GPIO2 13 GPIO1, DAI1_DATA2 25 GPIO18, DAO_MCLK GPIO11, SCP_CLK GPIO9, SCP_MOSI GPIO5, XMTA GPIO7, HS4 GND4 VDD2 25 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 8.3 CS48560,48-pin LQFP Pinout Diagram GPIO6, DAO2 _DATA0, HS3 GPIO5, DAO1_DATA3, X MTA GPIO3, DAO1_ DATA1, HS1 GPIO7, DAO2_D ATA1, HS4 GPIO4, DAO1_ DATA2, HS2 GPIO10, SCP__MISO / SDA GNDIO3 VDDIO3 37 GPIO8, SCP_CS# 38 GPOI12, SCP_IRQ# 39 GNDIO4 40 GPIO13, SCP_BSY#, EE_CS# 41 VDD3 42 XTAL_OUT 43 XTI 44 XTO 45 FI PLL_REF_RES 47 D GNDA 46 VDDA (3.3V) 48 10 11 N GPIO16, DAI1_DATA0, TM0, DSD0 GPIO0, DAI1_DATA1, TM1, DSD1 RESET# GNDIO1 Figure 14. CS48560, 48-Pin LQFP Pinout 26 (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL DAI1_LRCLK, DAI1_DATA4, DSD5 C DAI1_SCLK, DSD-CLK O VDDIO1 GND1 GND2 TEST DBDA DBCK 12 1 2 3 4 5 6 7 8 9 EN D TI EL A L PH D I RA 23 22 21 20 CS48560 48 LQFP FT 24 VDDIO2 DAO_SCLK GND3 DAO_LRCLK DAO1_DATA0, HS0 19 GNDIO2 18 GPIO15, DAI2_SCLK 17 GPIO14, DAI2_LRCLK 16 VDD1 15 GPIO17, DAI2_DATA0, DSD4 14 GPIO2, DAI1_DATA3, TM3, DSD3 13 GPIO1, DAI1_DATA2, TM2, DSD2 36 35 33 31 30 28 26 34 32 29 27 25 GPIO18, DAO_MCLK GPIO11, SCP_CLK GPIO9, SCP_MOSI GND4 VDD2 DS734A3 CS48500 Data Sheet 32-bit Audio Decoder DSP Family 9. Package Mechanical Drawings 9.1 48-pin LQFP Package Drawing 48 LD LQFP (7 x 7 x 1.4 mm body) C O A A1 A2 b D D1 e E E1 theta L L1 Number of Leads 48 MIN NOM MAX 1.60 0.05 0.15 1.35 1.40 1.45 0.17 0.22 0.27 9.00 BSC 7.00 BSC 0.50 BSC 9.00 BSC 7.00 BSC 0 7 0.45 0.60 0.75 1.00 REF N NOTES: 1) Reference document: JEDEC MS-026 2) All dimensions are in millimeters and controlling dimension is in millimeters. 3) D1 and E1 do not include mold flash which is 0.25 mm max. per side.A1 4) Dimension b does not include a total allowable dambar protrusion of 0.08 mm max. FI DS734A3 D EN D TI EL A L PH D I RA Figure 15. 48-Pin LQFP Package Drawing (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL 27 FT CS48500 Data Sheet 32-bit Audio Decoder DSP Family 10. Revision History Revision A1 A2 A3 Date JUL 2006 JUL 2006 DEC 5 2006 Advance release. Updated pinout definition for pins 26 and 27. Updated typical power numbers. Updated sections 2.0, 4.2.1, 5.8, Table 3, Table 4, to show new device numbering scheme. Updated sections 8.1, 8.2, 8.3. Changes C O N FI 28 D EN D TI EL A L PH D I RA (c)Copyright 2006 Cirrus Logic, Inc. CONFIDENTIAL DS734A3 FT |
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